The present invention relates to a semiconductor memory device having a data transmission circuit for transmitting data read out from memory cells to an output buffer via data transmission lines, and more particularly to a semiconductor memory device having an improved data transmission circuit for improvement of data reading time.
General semiconductor memory devices such as DRAM(Direct Random Access Memory), EPROM(Erasable Programmable Read Only Memory), SRAM(Static Random Access Memory) have a data transmission line for transmitting data read out from a plurality of memory cells to an output buffer. Since the data transmission line is in form a relatively long length for receiving data from the plurality of memory cells, it has capacitance impedance and resistance impedance, The resistance impedance of the data transmission line increases the voltage of data signal to be transmitted to the output buffer. The capacitance impedance of the data transmission line delays the data signal to be transmitted to the output buffer. The high voltage of data signal and the delay of data signal makes a driver connected between the data transmission line and the memory cell have a transistor with a large channel width, and makes the memory cells of the semiconductor memory device be separated into several blocks. The blocking of the memory cells reduces the power consumption of the semiconductor memory device, and the transistor with the large channel width improves the reading speed of the semiconductor memory device. However, the transistor with a large channel width included in the conventional semiconductor memory device adds parasitic capacitance impedance to the data transmission line, to limit the data transmission speed from the memory cell to the output buffer and the reading speed of the semiconductor memory device. The above problem of the conventional semiconductor memory device is described with reference to FIGS. 1 and 2.
FIG. 1 illustrates a conventional semiconductor memory device having first to nth memory blocks 10 to 14 in common connected to a true data transmission line 11 and a complementary data transmission line 13. Each of the first to nth memory blocks 10 to 14 includes j memory cell arrays each of which is composed of i memory cells for storing data, i data transmission stages for transmitting data from memory cells of the j memory cell arrays the true and complementary data transmission lines, i true block data lines for transmitting true data read out from each memory cell of the j memory cell arrays to the i data transmission stages, and i complementary block data lines for transmitting complementary data read out from each memory cell of the j memory cell arrays the i data transmission stages. Each of the first to nth memory blocks 10 to 14 further comprises i.times.j sense amplifiers respectively connected to the i.times.j memory cells for sensing and amplifying true and complementary data read out from the memory cells, i.times.j data switching NMOS transistors for switching amplified true data from the i.times.j sense amplifiers to the i true block data lines, and i.times.j data switching NMOS transistors for switching amplified complementary data from the i.times.j sense amplifiers to the i complementary block data lines. However, for the convenience of description, it is assumed that the ith memory block 12 has the jth memory cell array 16, i sense amplifiers and 24 respectively connected to i memory cells of the jth memory cell array 16, i data switching NMOS transistors Q1 and Q3 for respectively switching amplified true data from the i sense amplifiers 22 and 24 to the i true block data lines 15 and 17, i data switching NMOS transistors Q2 and Q4 for switching amplified complementary data from the sense amplifiers 22 and 24 to the complementary block data lines 19 and 21, and i data transmission stages 18 and 20 for respectively transmitting true and complementary data from the i true and complementary block data lines 15 to 21 to the true and complementary data transmission lines 11 and 13.
The first data transmission stage 18 included in the jth memory block 12 has two PMOS transistors Q5 and Q6 driven in response to a first pre-charge enable signal PRC supplied via a first control line 23. The two PMOS transistors Q5 and Q6 are turned on to supply a first power supply voltage Vcc from a first power supply Vcc to first true and complementary block data lines 15 and 19, when the pre-charge enable signal PRC has low logic (i.e., when the ith memory block 12 is selected). The first true and complementary block data lines 15 and 19 are pre-charged to the same voltage level as the first power supply voltage Vcc, until a jth column enable signal CEj supplied to the second control line 25 is changed from low logic to high logic as shown in FIG. 2A. With the jth column enable signal CEj of high logic, the true data generated in the first true block data line 15 has the same voltage level as the first power supply voltage Vcc as shown in FIG. 2B, when the first memory cell of the jth memory cell array 16 stores "1". Contrarily, when the first memory cell of the jth memory cell array 16 stores "0", a true data signal having a voltage level Vcc-.DELTA.V1 voltage-divided by the impedance of the NMOS transistor Q1 and the PMOS transistor Q5 is generated in the first true block data line 15. Also, with the jth column enable signal CEj of high logic, the complementary data generated in the first complementary block data line 19 has the same voltage level as the first power supply voltage Vcc, when the first memory cell of jth memory cell array 16 stores "0". When the first memory cell of the jth memory cell array 16 stores "1", a complementary data signal in a voltage level Vcc-.DELTA.V1 voltage-divided by the impedance of the NMOS transistor Q2 and the PMOS transistor Q6 is generated in the first complementary block data line 19.
The first data transmission stage 18 additionally has a NMOS transistor Q11 receiving the first amplification enable signal AE1 via a third control line 27 and a bit sense amplifier 26 driven by the NMOS transistor Q11. When the first amplification enable signal AE1 has high logic as shown in FIG. 2C, the NMOS transistor Q11 is turned on to supply the second power supply voltage GND from the second power supply GND to the bit sense amplifier 26. While the second power supply voltage GND is supplied via the NMOS transistor Q11, the bit sense amplifier 26 inverts and amplifies true and complementary data signals from the first true and complementary block data lines 15 and 19 and supplies the inverted and amplified true and complementary data signals to the first and second inverters 28 and 30, respectively. The true data generated in the bit sense amplifier 26 has high logic as shown in FIG. 2D, when "0" is stored in the first memory cell of the jth memory cell array 16. The inverted and amplified complementary data has high logic as shown in FIG. 2D, when "1" is stored in the first memory cell of the jth memory cell array 16. The first inverter 28 inverts the inverted and amplified true data signal from the bit sense amplifier 26 and supplies the inverted signal to drains of PMOS transistor Q7 and NMOS transistor Q8 constituting a parallel circuit. The PMOS transistor Q7 supplies the true data from the first inverter 28 to the true data transmission line 11 in response to the first data output enable bar signal DOEB1 of low logic supplied to its gate from the fourth control line 29. The NMOS transistor Q8 supplies the true data signal from the first inverter 28 to the true data transmission line 11 in response to the first data output enable signal DOE1 of high logic, such as FIG. 2E, supplied to its gate from the fifth control line 31. Meanwhile, the second inverter 30 inverts the inverted and amplified complementary data signal supplied from the bit sense amplifier 26 and supplies the inverted signal to the drains of PMOS transistor Q10 and NMOS transistor Q9 constituting a parallel circuit. The PMOS transistor Q10 supplies a complementary data signal from the third inverter 30 to the complementary data transmission line 13 in response to a first data output enable bar signal DOEB1 of low logic supplied to its gate from the fourth control line 29. The NMOS transistor Q9 supplies the complementary data signal from the second inverter 30 to the complementary data transmission line 13 in response to the first data output enable signal DOE1 of high logic supplied to its gate from the fifth control lien 31. As a result, the four MOS transistors Q7 to Q10 transmit the true and complementary data from the first and second inverters 28 and 30 to the true and complementary data transmission lines 11 and 13, as shown in FIG. 2F.
Meanwhile, the ith data transmission stage 20 functions to transmit true and complementary data signals from the ith true and complementary block data lines 17 and 21 to the true and complementary data transmission lines 11 and 13. To do this, the ith data transmission stage 20 has a bit sense amplifier 32, two inverters 34 and 36, four PMOS transistors Q12 to Q14, and Q17, and three NMOS transistors Q15, Q16 and Q18, which respectively have the same constitutions as those of the first data transmission stage 18. The description of the ith data transmission stage 20 is omitted since it has the same constitution and function except that the ith amplification enable signal AEi, data output enable bar signal DOEBi, and data output enable signal DOEi are entered from the sixth to eighth control lines 33 to 37, instead of the first amplification enable signal AE1, the first data output enable bar signal DOEB1, and the first data output enable signal DOE1 entering the first data transmission stage 18.
As described above, the conventional semiconductor memory device can rapidly transmit the data to the data transmission lines by the pairs of MOS transistors Q7 to Q10, and Q14 to Q17 having large channel width and connected in parallel. However, the conventional semiconductor memory device limits the transmission speed of data on the data transmission line to below a predetermined threshold speed due to the capacitance impedance of MOS transistors Q7 to Q10, and Q14 to Q17 with the large channel width, and cannot improve the reading speed to above a predetermined threshold speed.